In recent years, a ΔΣ TDC (Time-to-Digital Converter) which is required to measure a time difference between two repetitive clocks with high time resolution and by a simple circuit has been proposed. By configuring this ΔΣ TDC as a multi-bit circuit, finer measurement can be attained for an identical measurement time compared to a 1-bit circuit.
However, in the multi-bit circuit, since the number of delay elements increases, delay values of a plurality of delay elements may vary relatively. When such delay mismatch has occurred, if an output calculation is made intact, an output result becomes nonlinear, thus causing a measurement error.
Also, a method of making error correction by estimating error components of an internal DAC of a ΔΣ ADC in a digital manner has been reported. With this method, correction is attained by subtracting estimated error components at the output timing. However, this error correction method is not used in the TDC.